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SEMICONDUCTOR TECHNICAL DATA
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TMOS E-FET.TM High Energy Power FET D2PAK for Surface Mount
N-Channel Enhancement-Mode Silicon Gate
The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This advanced TMOS E-FET is designed to withstand high energy in the avalanche and commutation modes. This new energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for medium voltage, high speed switching applications in power supplies, converters and PWM motor controls. These devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. New Features of TMOS 7 * Ultra Low On-Resistance Provides Higher Efficiency * Reduced Gate Charge Features Common to TMOS 7 and TMOS E-FETS * Logic Level Gate Drive * Avalanche Energy Specified * Diode Characterized for Use in Bridge Circuits * IDSS and VDS(on) Specified at Elevated Temperature * Industry Standard D2PAK Surface Mount Package * Surface Mount Package Available in 24 mm, 13-inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Drain-to-Source Voltage Drain-to-Gate Voltage (RGS = 1.0 M) Gate-to-Source Voltage -- Continuous Gate-to-Source Voltage -- Non-Repetitive (tp 10 ms) Drain Current -- Continuous Drain Current -- Continuous @ 100C Drain Current -- Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (1) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = 60 Vdc, VGS = 5.0 Vdc, PEAK IL = 60 Apk, L = 0.3 mH, RG = 25 ) Thermal Resistance -- Junction to Case Thermal Resistance -- Junction to Ambient Thermal Resistance -- Junction to Ambient (1) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds (1) When surface mounted to an FR4 board using the minimum recommended pad size.
MTB71040L
TMOS POWER FET 60 AMPERES 100 VOLTS RDS(on) = 0.022 W
(R)
N-Channel D
CASE 418B-03, Style 2 D2PAK G S
Symbol VDSS VDGR VGS VGSM ID ID IDM PD
Value 100 100 20 25 60 48 210 242 1.61 3.0 - 55 to 175 540
Unit Vdc Vdc Vdc Vpk Adc Apk Watts W/C Watts C mJ
TJ, Tstg EAS RJC RJA RJA TL
0.62 62.5 50 260
C/W
C
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E-FET is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
(c) Motorola TMOS Motorola, Inc. 1999
Power MOSFET Transistor Device Data
1
MTB71040L
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 100 Vdc, VGS = 0 Vdc) (VDS = 100 Vdc, VGS = 0 Vdc, TJ =150C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (1) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 30 Adc) (VGS = 5.0 Vdc, ID = 30 Adc) Drain-to-Source On-Voltage (VGS = 10 Vdc, ID = 60 Adc) (VGS = 10 Vdc, ID = 30 Adc, TJ = 150C) Forward Transconductance (VDS = 8 Vdc, ID = 15 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 80 Vd , ID = 30 Adc, Vdc, Ad , ( VGS = 5.0 Vdc) Vdc, (VDD = 50 Vd ID = 30 Adc, Ad VGS = 5.0 Vdc, 5 0 Vdc RG = 1.4 ) ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (IS = 30 Adc, VGS = 0 Vdc) (IS = 30 Adc, VGS = 0 Vdc, TJ = 150C) Reverse Recovery Time (See Figure 14) ( (IS = 30 Adc, VGS = 0 Vdc, Ad , Vd , dIS/dt = 100 A/s) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) (1) Pulse Test: Pulse Width 300 s, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature. LD -- -- LS -- 7.5 -- 3.5 4.5 -- -- nH trr ta tb QRR VSD -- -- -- -- -- -- 0.81 0.65 155 100 55 0.87 1.0 -- -- -- -- -- C ns Vdc -- -- -- -- -- -- -- -- 15 215 60 130 67 10 42 36 30 430 120 260 90 -- -- -- nC ns (VDS = 25 Vdc, VGS = 0 Vdc, Vdc Vdc f = 1.0 MHz) Ciss Coss Crss -- -- -- 3000 625 140 4200 880 280 pF VGS(th) 1.0 -- RDS(on) -- -- VDS(on) -- -- gFS 30 -- -- 35 1.6 1.5 -- mhos 0.019 0.021 0.022 0.024 Vdc 1.5 5.5 2.0 -- Vdc mV/C Ohms V(BR)DSS 100 -- IDSS -- -- IGSS -- -- -- -- 10 100 100 nAdc -- 135 -- -- Vdc mV/C Adc Symbol Min Typ Max Unit
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Motorola TMOS Power MOSFET Transistor Device Data
MTB71040L
TYPICAL ELECTRICAL CHARACTERISTICS
120 110 ID, DRAIN CURRENT (AMPS) 100 90 80 70 60 50 40 30 20 10 0 0 1 2 3 4 5 6 7 8 9 10 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 3V VGS = 10 V 8V 6V 5V 4.5 V 120 TJ = 25C 4V ID, DRAIN CURRENT (AMPS) 110 100 90 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 - 55C 3.5 4 4.5 5 TJ = 100C 25C VDS 10 V
3.5 V
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
0.040 TJ = 100C 0.035 0.030 0.025 25C 0.020 0.015 0.010 0.005 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 ID, DRAIN CURRENT (AMPS) VGS = 10 V - 55C
RDS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS)
0.030 TJ = 25C 0.025 0.020 0.015 0.010 0.005 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 ID, DRAIN CURRENT (AMPS) 5V VGS = 10 V
Figure 3. On-Resistance versus Drain Current and Temperature
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
Figure 4. On-Resistance versus Drain Current and Gate Voltage
2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 -50 VGS = 10 V ID = 30 A
10,000 TJ = 150C 1000 IDSS, LEAKAGE (nA) 100C 100 25C 10
1 VGS = 0 V 0.1 -25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 70 80 90 100 110 TJ, JUNCTION TEMPERATURE (C) VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
3
MTB71040L
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
10,000 9000 8000 C, CAPACITANCE (pF) 7000 6000 5000 4000 3000 2000 1000 0 -10 Crss -5 VGS 0 VDS 5 10 15 20 25 Coss Crss Ciss Ciss VDS = 0 V VGS = 0 V TJ = 25C
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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Motorola TMOS Power MOSFET Transistor Device Data
MTB71040L
QT VGS VDS 10 9 8 7 6 5 4 3 2 1 0 0 Q3 Q1 Q2 ID = 30 A TJ = 25C 80 72 64 56 48 40 32 24 16 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 11 88 1000
100 t, TIME (ns)
tr tf td(off)
td(on) 10 VDD = 50 V ID = 30 A VGS = 5 V TJ = 25C 1 10 RG, GATE RESISTANCE (OHMS) 100
8 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 QG, TOTAL GATE CHARGE (nC)
1
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 15. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high
60 I S , SOURCE CURRENT (AMPS) 55 50 45 40 35 30 25 20 15 10 5 0 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) TJ = 25C VGS = 0 V
di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
Figure 10. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
MTB71040L
Standard Cell Density trr I S , SOURCE CURRENT High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
1000 VGS = 20 V SINGLE PULSE TC = 25C 100 100 ms EAS , SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)
600 550 500 450 400 350 300 250 200 150 100 50 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (C) 175 ID = 60 A
ID , DRAIN CURRENT (AMPS)
10 ms
10 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 0.1 1 10
1.0 ms 10 ms dc 100 1000
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
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Motorola TMOS Power MOSFET Transistor Device Data
MTB71040L
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE 0.01 1.00E-05 1.00E-04 1.00E-03 1.00E-02 t, TIME (s) 1.00E-01 1.00E+00 1.00E+01
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7
MTB71040L
PACKAGE DIMENSIONS
C E -B-
4
V
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 14.60 15.88 1.14 1.40
A
1 2 3
S
STYLE 2: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN
-T-
SEATING PLANE
K G D 3 PL 0.13 (0.005) H
M
J
DIM A B C D E G H J K S V
TB
M
CASE 418B-03 ISSUE C
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MTB71040L/D Motorola TMOS Power MOSFET Transistor Device Data

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